`timescale 1ns/100ps

module Mux2to1_1bit();

reg ip, self, enable;
wire op;

Mux2to1_1bit mux00(ip,self,op,enable);

initial begin
#0 ip=0; self=1; enable=0;
#10 ip=1; self=1; enable=0;
#20 ip=0; self=1; enable=1;
#30 ip=1; self=1; enable=1;
end

endmodule